`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/12 21:22:51
// Design Name: 
// Module Name: timer_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module timer_sim();
    reg clk = 1'b0;
    wire [3:0] high;
    wire [3:0] low;
    
    timer UUT(.clk_i(clk), .rst_i(1'b0), .highdigit_o(high), .lowdigit_o(low));
    
    always #1 begin 
        clk = ~clk;
    end
     
    initial begin
        #2147483647 $stop;
    end
endmodule
